This invention relates to semiconductor devices, and more particularly to sense amplifier circuits for dynamic read/write memory devices.
Dynamic MOS read/write memory devices have been constructed generally as shown in U.S. Pat. No. 4,081,701 (a 16K dynamic RAM) issued to White, McAdams and Redwine, or U.S. Pat. No. 4,239,993 (a 64K dynamic RAM) issued to McAlexander, White and Rao, both assigned to Texas Instruments. When memory devices of this type are manufactured in higher densities, such as 256K and 1-Megabit and beyond, the problem of limiting the peak current supplied to the chip becomes formidible.
In a 1-Megabit DRAM that is refreshed at 512 per period, there are 2048 sense amplifiers which flip at the same time during an active cycle. Each one of these requires current to charge a bit line to Vdd, or discharge a bit line to Vss, or both, depending upon the precharge level. The voltage supply to the chip thus sees a very large current spike in a short time period; as the access time is increased, the magnitude of the current spike increases. In U.S. Pat. No. 4,050,061, issued to Nori Kitagawa, assigned to Texas Instruments, a technique is disclosed for limiting the peak current by partitioning the array into blocks and activating the sense amplifiers fully in only the addressed block; the other blocks are activated at a lower level and operate more slowly.
It is the principal object of this invention to provide an improved sense amplifier circuit for high density dynamic RAM devices, particularly for high-speed, low power devices. Another object is to provide a sense amplifier circuit for a CMOS dynamic RAM in which the peak current is minimized. A further object is to provide high speed, low current circuitry for semiconductor devices which contain bistable or latch circuits and the like.